1. Technical Field
The present invention relates to semiconductor memory apparatus, and more particularly, to an apparatus and method for controlling an active cycle of semiconductor memory apparatus.
2. Related Art
FIG. 1 shows the configuration of an apparatus for controlling an active cycle of semiconductor memory apparatus, particularly, a synchronous semiconductor memory apparatus supporting an asynchronous mode, according to the related art.
The apparatus includes a first pulse generating unit 11 to which a chip selection signal CS is input, a first transistor M1 that has a source connected to a power supply terminal and a gate connected to an output terminal of the first pulse generating unit 11, a first inverter IV1 that includes second and third transistors M2 and M3 having gates to which a clock signal CLK is input and is connected between the first transistor M1 and a ground terminal, a first latch 12 that is connected to an output terminal of the first inverter IV1, a second inverter IV2 that is connected to an output terminal of the first latch 12, a second pulse generating unit 13 that is connected to an output terminal of the second inverter IV2, a first NAND gate ND1 to which the clock signal CLK and an active address ADV are input, a third pulse generating unit 14 to which the output of the first NAND gate ND1 is input, a fourth pulse generating unit 15 to which a normal active signal N_ACT is input, a fourth transistor M4 that has a gate to which the output of the second pulse generating unit 13 is input and a source connected to the ground terminal, a fifth transistor M5 that has a gate to which the output of the third pulse generating unit 14 is input, a source connected to the ground terminal, and a drain connected to the drain of the fourth transistor M4, a third inverter IV3 that includes two transistors having gates to which the output of the fourth pulse generating unit 15 is input and is connected to the power supply terminal and the drain of the fourth transistor M4, a second latch 16 that is connected to an output terminal of the third inverter IV3, a fourth inverter IV4 to which a pre-charge signal PCG is input, an eighth transistor M8 that has a source connected to the power supply terminal and a gate to which the output of the fourth inverter IV4 is input, a ninth transistor M9 that has a drain connected to the eighth transistor M8, a gate to which a delayed normal active signal N_ACTd is input, and a source connected to the ground terminal, a third latch 17 that is connected to a connection node of the eighth transistor M8 and the ninth transistor M9, a fifth inverter IV5 that is connected to an output terminal of the third latch 17, a second NAND gate ND2 to which the output of the fifth inverter IV5 and the output of the second latch 16 are input, a sixth inverter IV6 to which the output of the second NAND gate ND2 is input, and a delay element 18 that receives the output of the sixth inverter IV6 and outputs a row active signal R_ACT and the delayed normal active signal N_ACTd.
When high-level signals are input, the first and fourth pulse generating units 11 and 15 generate low pulses. When a high-level signal is input, the second pulse generating unit 13 generates a high pulse. When a low-level signal is input, the third pulse generating unit 14 generates a high pulse.
The first to third latches 12, 16, and 17 each include two inverters that invert input signals, output the inverted signals, and feed back the output signal to the input terminals thereof.
Next, the operation of the apparatus for controlling an active cycle of a semiconductor memory apparatus according to the related art will be described with reference to FIGS. 1 and 2.
When the chip selection signal CS is enabled, that is, turns to a high level, as shown in FIG. 2, the first pulse generating unit 11 generates a low pulse to cause the first transistor M1 to be turned on.
When the clock signal CLK is at the low level, as shown in FIG. 2, a high-level signal is output from the first inverter IV1, and the operational mode determination signal MIX_CON is enabled, that is, turns to a high level through the first latch 12 and the second inverter IV2.
The semiconductor memory apparatus according to the related art supports an asynchronous mode. Therefore, once the chip selection signal CS is enabled, the operational mode determination signal MIX_CON is enabled, that is, turns to a high level to execute the asynchronous mode regardless of the input of the clock signal CLK.
The enabled operational mode determination signal MIX_CON causes a ready signal READY to be enabled, that is, to turn to a high level, as shown in FIG. 2.
Since the operational mode determination signal MIX_CON is at the high level, the second pulse generating unit 13 generates a high pulse, which causes the fourth transistor M4 to be turned on. At that time, since the normal active signal N_ACT is disabled, that is, the normal active signal N_ACT is at a low level, the fourth pulse generating unit 15 outputs a high-level signal, and thus the third inverter IV3 outputs a low-level signal, which causes the ready signal READY from the second latch 16 to be enabled, that is, to turn to a high level.
The enabled ready signal READY causes the normal active signal N_ACT to be enabled, that is, to change to a high level, and thus the row active signal R_ACT and the delayed normal active signal N_ACTd are enabled, as shown in FIG. 2.
Since the ready signal READY is at the high level and PA output from the fifth inverter IV5 is also at the high level, the normal active signal N_ACT is enabled, that is, turns to a high level through the second NAND gate ND2 and the sixth inverter IV6, and the row active signal R_ACT and the delayed normal active signal N_ACTd are enabled through the delay element 18. At that time, PA turns to a high level by the pre-charge signal PCG and turns to a low level by the delayed normal active signal N_ACTd. PA is kept at the high level until an active operation is performed, as shown in FIG. 2.
When the normal active signal N_ACT is enabled, that is, turns to a high level, the ready signal READY is disabled, that is, turns to a low level, as shown in FIG. 2.
Since the normal active signal N_ACT is at the high level, the fourth pulse generating unit 15 outputs a low pulse, and thus the ready signal READY is disabled, that is, turns to a low level through the third inverter IV3 and the second latch 16.
Meanwhile, when the clock signal CLK is input, the operational mode determination signal MIX_CON is disabled, that is, turns to a low level, and a synchronous active signal CLK_ACT is enabled, that is, turns to a high level, as shown in FIG. 2.
When the clock signal CLK is toggled from the low level to the high level, the first inverter IV1 outputs a low-level signal, and the operational mode determination signal MIX_CON turns to a low level through the first latch 12 and the second inverter IV2. In addition, when the effective address ADV is enabled, that is, changes to a high level, the first NAND gate ND1 outputs a low-level signal, and the synchronous active signal CLK_ACT is enabled, that is, turns to a high level through the third pulse generating unit 14.
When the synchronous active signal CLK_ACT is enabled, that is, turns to the high level, the ready signal READY is enabled, that is, turns to a high level, and thus the pre-charge signal PCG is enabled, that is, turns to a high level for executing pre-charging, which causes PA to turn to a high level.
When the pre-charge signal PCG turns to the high level, the eighth transistor M8 is turned on, which causes PA to turn to the high level through the third latch 17 and the fifth inverter IV5.
When the ready signal READY and PA are enabled, that is, turn to the high level, the normal active signal N_ACT is enabled, that is, turns to a high level, as shown in FIG. 2.
When the normal active signal N_ACT is enabled, that is, turns to the high level, the ready signal READY is disabled, that is, turns to a low level, and the delayed normal active signal N_ACTd and the row active signal R_ACT are enabled, that is, turn to a high level, as shown in FIG. 2.
As described above, in the semiconductor memory apparatus according to the related art, two active cycles, that is, an active cycle in which the semiconductor memory apparatus is operated in the asynchronous mode at the beginning and an active cycle in which the semiconductor memory is operated in the synchronous mode in response to an input clock, are executed.
Therefore, the semiconductor memory apparatus according to the related art has a problem in that two active cycles are executed in the synchronous mode, resulting in a low operational speed and high current consumption.